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1. general description the 74lvc821a is a high performance, low power, low voltage si-gate cmos device and superior to most advanced cmos compatible ttl families. inputs can be driven from either 3.3 v or 5 v devices. in 3-state operation, outputs can handle 5 v. this feature allows the use of these devices as translators in a mixed 3.3 v and 5 v environment. the 74lvc821a is a 10-bit d-type ?ip-?op featuring separate d-type inputs for each ?ip-?op and 3-state outputs for bus-oriented applications. a clock input (pin cp) and an output enable input (pin oe) are common to all ?ip-?ops. the ten ?ip-?ops will store the state of their individual d-inputs that meet the set-up and hold times requirements on the low-to-high cp transition. when pin oe is low, the contents of the ten ?ip-?ops is available at the outputs. when pin oe is high, the outputs go to the high-impedance off-state. operation of the oe inputs does not affect the state of the ?ip-?ops. 2. features n 5 v tolerant inputs and outputs; for interfacing with 5 v logic n wide supply voltage range from 1.2 v to 3.6 v n inputs accept voltages up to 5.5 v n cmos low power consumption n direct interface with ttl levels n flow-through pin-out architecture n 10-bit positive edge-triggered register n independent register and 3-state buffer operation n complies with jedec standard jesd8-b n esd protection: u hbm eia/jesd22-a114-b exceeds 2000 v u mm eia/jesd22-a115-a exceeds 200 v. n speci?ed from - 40 c to +85 c and - 40 c to +125 c. 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs; positive-edge trigger; 3-state rev. 03 11 may 2004 product data sheet
9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 2 of 20 philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs 3. quick reference data [1] c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. [2] the condition is v i = gnd to v cc . 4. ordering information table 1: quick reference data gnd = 0 v; t amb = 25 c; t r = t f 2.5 ns. symbol parameter conditions min typ max unit t phl , t plh propagation delay cp to qn c l = 50 pf; v cc = 3.3 v - 3.7 - ns t pzh , t pzl 3-state output enable time oe to qn c l = 50 pf; v cc = 3.3 v - 3.5 - ns t phz , t plz 3-state output disable time oe to qn c l = 50 pf; v cc = 3.3 v - 3.0 - ns f max maximum clock frequency c l = 50 pf; v cc = 3.3 v - 200 - mhz c i input capacitance - 5.0 - pf c pd power dissipation capacitance per gate v cc = 3.3 v [1] [2] outputs enabled - 17 - pf outputs disabled - 11 - pf table 2: ordering information type number package temperature range name description version 74lvc821ad - 40 c to +125 c so24 plastic small outline package; 24 leads; body width 7.5 mm sot137-1 74lvc821adb - 40 c to +125 c ssop24 plastic shrink small outline package; 24 leads; body width 5.3 mm sot340-1 74lvc821apw - 40 c to +125 c tssop24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 74lvc821abq - 40 c to +125 c dhvqfn24 plastic dual in-line compatible thermal enhanced very thin quad ?at package; no leads; 24 terminals; body 3.5 5.5 0.85 mm sot815-1
9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 3 of 20 philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs 5. functional diagram fig 1. functional diagram. fig 2. logic symbol. fig 3. iec logic symbol. 001aaa679 3-state outputs ff0 to ff9 q0 q3 q4 q5 q6 q7 q8 q9 14 15 16 17 18 19 20 23 d0 d3 d4 d5 d6 d7 d8 d9 cp oe 11 13 1 10 9 8 7 6 5 q1 q2 21 22 d1 d2 4 3 2 001aaa677 d0 d1 d2 d3 d4 d5 d6 d9 oe cp q0 q1 q2 q3 q4 q5 q6 q9 13 1 14 17 18 19 20 21 22 23 11 8 7 d7 d8 q7 q8 15 16 10 9 6 5 4 3 2 001aaa678 14 17 18 19 20 21 22 13 c1 1 en 1d 23 11 8 7 6 5 4 3 2 16 9 15 10
9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 4 of 20 philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs fig 4. logic diagram. 001aaa681 q4 d4 q3 d3 q2 d2 q1 d1 q0 d0 d ff1 q cp cp d ff2 q cp d ff3 q cp d ff4 q cp d ff5 q cp d ff6 q cp d ff7 q cp d ff10 q cp oe q5 d5 q6 d6 q9 d9 d ff8 q cp d ff9 q cp q7 d7 q8 d8
9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 5 of 20 philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs 6. pinning information 6.1 pinning 6.2 pin description (1) the die substrate is attached to this pad using conductive die attach material. it can not be used as a supply pin or input. fig 5. pin con?guration so24 and (t)ssop24. fig 6. pin con?guration dhvqfn24. 821a oe v cc d0 q0 d1 q1 d2 q2 d3 q3 d4 q4 d5 q5 d6 q6 d7 q7 d8 q8 d9 q9 gnd cp 001aaa676 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 1 2 3 4 5 6 7 8 9 d0 d1 d2 d3 d4 d5 d6 d7 23 22 21 20 19 18 17 16 q1 q0 q2 q3 q4 q5 q6 q7 10 11 d8 d9 15 14 q8 q9 24 oe v cc 12 13 gnd top view cp gnd (1) 001aaa680 table 3: pin description symbol pin description oe 1 output enable input (active low) d0 2 data input d1 3 data input d2 4 data input d3 5 data input d4 6 data input d5 7 data input d6 8 data input d7 9 data input d8 10 data input d9 11 data input
9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 6 of 20 philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs 7. functional description [1] h = high voltage level; h = high voltage level one set-up time prior to the low-to-high cp transition; l = low voltage level; l = low voltage level one set-up time prior to the low-to-high cp transition; z = high-impedance off-state; l = low voltage level one set-up time prior to the low-to-high cp transition; nc = no change; x = dont care. 8. limiting values gnd 12 ground (0 v) cp 13 clock input (low-to-high, edge-triggered) q9 14 3-state ?ip-?op output q8 15 3-state ?ip-?op output q7 16 3-state ?ip-?op output q6 17 3-state ?ip-?op output q5 18 3-state ?ip-?op output q4 19 3-state ?ip-?op output q3 20 3-state ?ip-?op output q2 21 3-state ?ip-?op output q1 22 3-state ?ip-?op output q0 23 3-state ?ip-?op output v cc 24 supply voltage table 3: pin description continued symbol pin description table 4: function table [1] operating mode input internal ?ip-?ops output oe cp dn qn load and read register l - ill l - hhh load register and disable outputs h - ilz h - hhz hold l h or l x nc nc table 5: limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage - 0.5 +6.5 v i ik input diode current v i <0 v - - 50 ma v i input voltage [1] - 0.5 +6.5 v i ok output diode current v o >v cc or v o <0 v - 50 ma
9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 7 of 20 philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] for so24 package: above 70 c derate linearly with 8 mw/k. for ssop24 and tssop24 packages: above 60 c derate linearly with 5.5 mw/k. for dhvqfn24 package: above 60 c derate linearly with 4.5 mw/k. 9. recommended operating conditions 10. static characteristics v o output voltage high or low state [1] - 0.5 v cc + 0.5 v 3-state [1] - 0.5 +6.5 v i o output source or sink current v o = 0 v to v cc - 50 ma i cc , i gnd v cc or gnd current - 100 ma t stg storage temperature - 65 + 150 c p tot power dissipation t amb = - 40 c to +125 c [2] - 500 mw table 5: limiting values continued in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit table 6: operating conditions symbol parameter conditions min typ max unit v cc supply voltage for maximum speed performance 2.7 - 3.6 v for low-voltage applications 1.2 - 3.6 v v i input voltage 0 - 5.5 v v o output voltage high or low state 0 - v cc v 3-state 0 - 5.5 v t amb operating ambient temperature in free air - 40 - +125 c t r , t f input rise and fall times v cc = 1.2 v to 2.7 v 0 - 20 ns/v v cc = 2.7 v to 3.6 v 0 - 10 ns/v table 7: static characteristics at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit t amb = - 40 c to +85 c [1] v ih high-level input voltage v cc = 1.2 v v cc --v v cc = 2.7 v to 3.6 v 2.0 - - v v il low-level input voltage v cc = 1.2 v - - gnd v v cc = 2.7 v to 3.6 v - - 0.8 v
9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 8 of 20 philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs v oh high-level output voltage v i =v ih or v il i o = - 100 m a; v cc = 2.7 v to 3.6 v [2] v cc - 0.2 v cc -v i o = - 12 ma; v cc = 2.7 v v cc - 0.5 - - v i o = - 18 ma; v cc = 3.0 v v cc - 0.6 - - v i o = - 24 ma; v cc = 3.0 v v cc - 0.8 - - v v ol low-level output voltage v i =v ih or v il i o = 100 m a; v cc = 2.7 v to 3.6 v [2] - gnd 0.2 v i o = 12 ma; v cc = 2.7 v - - 0.4 v i o = 24 ma; v cc = 3.0 v - - 0.55 v i li input leakage current v i = 5.5 v or gnd; v cc = 3.6 v - 0.1 5 m a i oz 3-state output off-state current v i =v ih or v il ; v o = 5.5 v or gnd; v cc = 3.6 v - 0.1 5 m a i off power-off leakage supply current v i or v o = 5.5 v; v cc = 0 v - 0.1 10 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 a; v cc = 3.6 v - 0.1 10 m a d i cc additional quiescent supply current per pin v i =v cc - 0.6 v; i o = 0 a; v cc = 2.7 v to 3.6 v [2] - 5 500 m a c i input capacitance - 5.0 - pf t amb = - 40 c to +125 c v ih high-level input voltage v cc = 1.2 v v cc --v v cc = 2.7 v to 3.6 v 2.0 - - v v il low-level input voltage v cc = 1.2 v - - 0 v v cc = 2.7 v to 3.6 v - - 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 100 m a; v cc = 2.7 v to 3.6 v v cc - 0.3 - - v i o = - 12 ma; v cc = 2.7 v v cc - 0.65 - - v i o = - 18 ma; v cc = 3.0 v v cc - 0.75 - - v i o = - 24 ma; v cc = 3.0 v v cc - 1--v v ol low-level output voltage v i =v ih or v il i o = 100 m a; v cc = 2.7 v to 3.6 v - - 0.3 v i o = 12 ma; v cc = 2.7 v - - 0.6 v i o = 24 ma; v cc = 3.0 v - - 0.8 v i li input leakage current v i = 5.5 v or gnd; v cc = 3.6 v - - 20 m a i oz 3-state output off-state current v i =v ih or v il ; v o = 5.5 v or gnd; v cc = 3.6 v -- 20 m a i off power-off leakage supply current v i or v o = 5.5 v; v cc = 0 v - - 20 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 a; v cc = 3.6 v --40 m a d i cc additional quiescent supply current per pin v i =v cc - 0.6 v; i o = 0 a; v cc = 2.7 v to 3.6 v - - 5000 m a table 7: static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit
9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 9 of 20 philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs [1] all typical values are measured t amb =25 c. [2] these typical values are measured at v cc = 3.3 v. 11. dynamic characteristics table 8: dynamic characteristics gnd = 0 v; t r =t f 2.5 ns; c l = 50 pf; r l = 500 w ; for test circuit see figure 10 symbol parameter conditions min typ max unit t amb = - 40 c to +85 c [1] t phl , t plh propagation delay cp to qn see figure 7 v cc = 1.2 v - 18 - ns v cc = 2.7 v 1.5 - 8.5 ns v cc = 3.0 v to 3.6 v [2] 1.5 3.7 7.3 ns t pzh , t pzl 3-state output enable time oe to qn see figure 9 v cc = 1.2 v - 20 - ns v cc = 2.7 v 1.5 - 8.8 ns v cc = 3.0 v to 3.6 v [2] 1.3 3.5 7.6 ns t phz , t plz 3-state output disable time oe to qn see figure 9 v cc = 1.2 v - 9.0 - ns v cc = 2.7 v 1.5 - 6.8 ns v cc = 3.0 v to 3.6 v [2] 1.5 3.0 6.2 ns t w clock pulse width high or low see figure 7 v cc = 1.2 v - - - ns v cc = 2.7 v 3.3 - - ns v cc = 3.0 v to 3.6 v [2] 3.3 1.7 - ns t su set-up time dn to cp see figure 8 v cc = 1.2 v - - - ns v cc = 2.7 v 0.9 - - ns v cc = 3.0 v to 3.6 v [2] 1.9 0.6 - ns t h hold time dn to cp see figure 8 v cc = 1.2 v - - - ns v cc = 2.7 v 1.5 - - ns v cc = 3.0 to 3.6 v [2] 1.5 0.0 - ns f max maximum clock frequency see figure 7 v cc = 1.2 v - - - mhz v cc = 2.7 v 150 - - mhz v cc = 3.0 v to 3.6 v [2] 150 200 - mhz t sk(0) skew v cc = 3.0 v to 3.6 v [3] - - 1.0 ns c pd power dissipation capacitance per gate v cc = 3.3 v [4] [5] outputs enabled - 17 - pf outputs disabled - 11 - pf
9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 10 of 20 philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs [1] all typical values are measured t amb =25 c. [2] these typical values are measured at v cc = 3.3 v. [3] skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. [4] c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. [5] the condition is v i = gnd to v cc . t amb = - 40 c to +125 c t phl , t plh propagation delay cp to qn see figure 7 v cc = 1.2 v - - - ns v cc = 2.7 v 1.5 - 11.0 ns v cc = 3.0 v to 3.6 v 1.5 - 9.5 ns t pzh , t pzl 3-state output enable time oe to qn see figure 9 v cc = 1.2 v - - - ns v cc = 2.7 v 1.5 - 11.0 ns v cc = 3.0 v to 3.6 v 1.3 - 9.5 ns t phz , t plz 3-state output disable time oe to qn see figure 9 v cc = 1.2 v - - - ns v cc = 2.7 v 1.5 - 8.5 ns v cc = 3.0 v to 3.6 v 1.5 - 8.0 ns t w clock pulse width high or low see figure 7 v cc = 1.2 v - - - ns v cc = 2.7 v 3.3 - - ns v cc = 3.0 v to 3.6 v 3.3 - - ns t su set-up time dn to cp see figure 8 v cc = 1.2 v - - - ns v cc = 2.7 v 0.9 - - ns v cc = 3.0 v to 3.6 v 1.9 - - ns t h hold time dn to cp see figure 8 v cc = 1.2 v - - - ns v cc = 2.7 v 1.5 - - ns v cc = 3.0 v to 3.6 v 1.5 - - ns f max maximum clock frequency see figure 7 v cc = 1.2 v - - - mhz v cc = 2.7 v 150 - - mhz v cc = 3.0 v to 3.6 v 150 - - mhz t sk(0) skew v cc = 3.0 v to 3.6 v [3] - - 1.0 ns table 8: dynamic characteristics continued gnd = 0 v; t r =t f 2.5 ns; c l = 50 pf; r l = 500 w ; for test circuit see figure 10 symbol parameter conditions min typ max unit
9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 11 of 20 philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs 12. waveforms measurement points are given in t ab le 9 . v ol and v oh are the typical output voltage drop that occur with the output load. fig 7. clock (cp) to output (qn) propagation delays, the clock pulse width and the maximum clock pulse frequency. table 9: measurement points supply voltage input output v cc v m v m < 2.7 v 0.5 v cc 0.5 v cc 3 2.7 v 1.5 v 1.5 v measurement points are given in t ab le 10 . v ol and v oh are the typical output voltage drop that occur with the output load. the shaded areas indicate when the input is permitted to change for predicable output performance. fig 8. data set-up and hold times for the dn input to the cp input. mna894 cp input qn output t phl t plh t w 1/f max v m v oh v i gnd v ol v m mna202 gnd gnd t h t h t su t su v m v m v m v i v oh v ol v i qn output cp input dn input
9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 12 of 20 philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs table 10: measurement points supply voltage input output v cc v m v m < 2.7 v 0.5 v cc 0.5 v cc 3 2.7 v 1.5 v 1.5 v measurement points are given in t ab le 11 . v ol and v oh are the typical output voltage drop that occur with the output load. fig 9. 3-state enable and disable times. table 11: measurement points supply voltage input output v cc v m v m v x v y < 2.7 v 0.5 v cc 0.5 v cc v ol + 0.1 v cc v oh - 0.1 v cc 3 2.7 v 1.5 v 1.5 v v ol + 0.3 v v oh - 0.3 v data test circuit (see t ab le 12 ). r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. fig 10. load circuitry for switching times. mgu775 t plz t phz outputs disabled outputs enabled v y v x outputs enabled qn output low-to-off off-to-low qn output high-to-off off-to-high oe input v i v ol v oh v cc v m v m gnd gnd t pzl t pzh v m v m v ext v cc v i v o mna616 d.u.t. c l r t r l r l pulse generator
9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 13 of 20 philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs [1] the circuit performs better when r l = 1000 w . table 12: test data supply voltage input load v ext v cc v i c l r l t plh , t phl t pzh , t phz t pzl , t plz 1.2 v v cc 50 pf 500 w [1] open gnd 2 v cc 2.7 v 2.7 v 50 pf 500 w open gnd 2 v cc 3.0 v to 3.6 v 2.7 v 50 pf 500 w open gnd 2 v cc
9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 14 of 20 philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs 13. package outline fig 11. package outline so24. unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot137-1 x 12 24 w m q a a 1 a 2 b p d h e l p q detail x e z c l v m a 13 (a ) 3 a y 0.25 075e05 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.61 0.60 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 e 1 0 5 10 mm scale so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1 99-12-27 03-02-19
philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs 9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 15 of 20 fig 12. package outline ssop24. unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 0.8 0.4 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 sot340-1 mo-150 99-12-27 03-02-19 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 112 24 13 0.25 y pin 1 index 0 2.5 5 mm scale ssop24: plastic shrink small outline package; 24 leads; body width 5.3 mm sot340-1 a max. 2
philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs 9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 16 of 20 fig 13. package outline tssop24. unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 0.4 0.3 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot355-1 mo-153 99-12-27 03-02-19 0.25 0.5 0.2 w m b p z e 112 24 13 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 a max. 1.1
9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 17 of 20 philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs fig 14. package outline dhvqfn24. references outline version european projection issue date iec jedec jeita note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. sot815-1 - - - - - - - - - 03-04-29 sot815-1 0 2.5 5 mm scale b y y 1 c c a c c b v m w m e 1 e 2 terminal 1 index area terminal 1 index area x unit a (1) max. a 1 bc e e h l e 1 y w v mm 1 0.05 0.00 0.30 0.18 0.5 4.5 e 2 1.5 0.2 2.25 1.95 d h 4.25 3.95 0.05 0.05 y 1 0.1 0.1 dimensions (mm are the original dimensions) 0.5 0.3 d (1) 5.6 5.4 e (1) 3.6 3.4 d e b a e dhvqfn24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm a a 1 c detail x e h l d h 2 23 11 14 13 12 1 24
9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 18 of 20 philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs 14. revision history table 13: revision history document id release date data sheet status change notice order number supersedes 74lvc821a_3 20040511 product data - 9397 750 13276 74lvc821a_2 modi?cations: ? figure 4 : corrected. 74lvc821a_2 20040415 product data - 9397 750 13047 74lvc821a_1 74lvc821a_1 19980925 product speci?cation - 9397 750 04584 -
philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs 9397 750 13276 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 11 may 2004 19 of 20 15. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 17. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 18. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2004 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 11 may 2004 document order number: 9397 750 13276 published in the netherlands philips semiconductors 74lvc821a 10-bit d-type ?ip-?op with 5 v tolerant inputs/outputs 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 recommended operating conditions. . . . . . . . 7 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 7 11 dynamic characteristics . . . . . . . . . . . . . . . . . . 9 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 15 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 16 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 17 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 18 contact information . . . . . . . . . . . . . . . . . . . . 19

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